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| Wafer-Level Packaging Symposium 2025 |
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Wafer-Level Packaging Symposium 2025 |
293 days left
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| Wafer-Level Packaging Symposium |
| Dates:
Tuesday, February 18, 2025 - Thursday, February 20, 2025
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| Venue: Hyatt Regency San Francisco Airport,
San Francisco CA,
United States |
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The Wafer-Level Packaging Symposium will bring together the semiconductor industry's most respected authorities to address all aspects of wafer-level, 3D device packaging, advanced manufacturing & test technologies.
Addressing wafer-level packaging, 3D, and Advanced Manufacturing & Test technologies, the Wafer-Level Packaging Symposium will be at the forefront of packaging technology evolution. The conference will feature an international audience gathering in the heart of Silicon Valley to immerse themselves in the latest technology and business trends. This event is produced by SMTA, the distinguished global association representing electronic assembly and manufacturing professionals.
The conference comprises three parallel technical tracks with 2.5 days of presentations on Wafer-Level Packaging, 3D Integration, and Advanced Manufacturing & Test. Professional Development Courses, keynote speakers, and panel discussions are offered by world-class experts and enable attendees to broaden their technical knowledge. The technical program includes a two-day expo where exhibitors showcase their latest technologies and products.
The conference provides a collective network of'industry professionals, including vendors from leading semiconductor companies, foundries, and OSATs, as well as key technology, equipment, and materials suppliers in the exhibit area. Attendees will be inspired by the quantity and quality of the featured new developments and emerging technologies.
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Website: https://smta.org/mpage/wafer
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