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IWLPC 2018
IWLPC 2018

IWLPC 2018

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15th International Wafer Level Packaging Conference
Dates: Tuesday, October 23, 2018 - Thursday, October 25, 2018
Venue: DoubleTree by Hilton San Jose, San Francisco CA, United States
SMTA and Chip Scale Review are pleased to announce the Annual International Wafer-Level Packaging Conference and Tabletop Exhibition. IWLPC brings together some of the semiconductor industry's most respected authorities addressing all aspects of wafer-level, 3D, TSV, and MEMS device packaging and manufacturing.

Website: http://www.iwlpc.com/
Venues
DoubleTree by Hilton Hotel San Jose
2050 Gateway Place, San Jose, California, 95110, San Jose CA
United States
Tel: +1-408-453-4000
http://doubletree.hilton.com/
Organizers
Surface Mount Technology Association (SMTA)
5200 Willson Road, Suite 215, Edina, MN 55424, Minneapolis
United States
Tel: +1-952-920.7682
http://www.smta.org/
Future Dates:
Wafer-Level Packaging Symposium 20232/14/2023 - 2/16/2023 San Francisco CA, United States
Wafer-Level Packaging Symposium 20262/17/2026 - 2/19/2026 San Francisco CA, United States
Wafer-Level Packaging Symposium 20272/9/2027 - 2/11/2027 San Francisco CA, United States
Wafer-Level Packaging Symposium 2028 San Francisco CA, United States
Previous Dates:
IWLPC 201610/18/2016 - 10/20/2016 San Francisco CA, United States
IWLPC 201510/13/2015 - 10/15/2015 San Francisco CA, United States
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